A phase-locked loop (PLL) is a feedback-based control system that generates an output signal having a phase that, through the feedback loop control, is driven into a fixed phase relationship with an input reference signal. Phase locked loops are used in frequency synthesizers, data transmission and recovery devices, and other applications. As illustrated in FIG. 1, a conventional PLL 10 includes a phase-frequency detector (PFD) 12, a loop filter 14, a voltage-controlled oscillator (VCO) 16, and a frequency divider 18. The PLL 10 outputs a signal (F_OUT) that has a frequency generated by VCO 16. Frequency divider 18 divides the frequency of F_OUT and provides the resulting divided-frequency (clock) signal (DIVCLK) to PFD 12, which also receives a reference clock signal (REFCLK). In response to the reference clock signal and the divided-frequency signal, PFD 12 provides an Up signal and a Down signal to loop filter 14. As described in further detail below, the Up and Down signals are digital pulses. In response to the Up and Down signals, loop filter 14 provides an analog voltage signal (V_CNTRL) that controls the output signal frequency of VCO 16. That is, the frequency of F_OUT is proportional to the analog voltage signal. More specifically, loop filter 14 includes a charge pump or similar circuit that drives current into the filter circuitry in response to the Up signal and draws current from the filter circuitry in response to the Down signal. Accordingly, the difference between the pulse widths of the Up and Down signals (i.e., Up-Down) represents the phase error and controls loop filter 14.
Phase lock is achieved when the rising edge of the divided-frequency clock signal and the rising edge of the reference clock signal are aligned, i.e., corresponding rising edges of the two signals repeatedly occur simultaneously.
As illustrated in FIG. 2, a conventional PFD 12 includes two D-type flip-flops 20 and 22 and a NAND gate 24. Flip-flop 20 outputs the above-referenced Up signal. Flip-flop 22 outputs the above-referenced Down signal. A high or logic-“1” is clocked into flip-flop 20 upon a rising edge of the reference clock signal. A high or logic-“1” is clocked into flip-flop 22 upon a rising edge of the divided-clock signal. When a logic-“1” is clocked into each of flip-flops 20 and 22, NAND gate 24 applies a reset pulse to each of flip-flops 20 and 22, resetting them to a value of logic-“0”. Accordingly, in an instance in which the rising edge of the reference clock leads, i.e., occurs before, the rising edge of the divided-frequency clock, PFD 12 generates an Up signal having a pulse width that is proportional to the amount of time by which the rising edge of the reference clock signal leads the rising edge of the divided-frequency clock signal. Conversely, in an instance in which the rising edge of the divided-frequency clock signal leads the rising edge of the reference clock signal, PFD 12 generates a Down signal having a pulse width that is proportional to the amount of time by which the rising edge of the divided-frequency clock signal leads the rising edge of the reference clock signal. The difference between Up and Down pulse widths represents the phase error that loop filter 14 uses to adjust the PLL loop to drive the phase error to zero.
To conserve power in an electronic device such as an integrated circuit, control circuitry in the device can turn off power-consuming circuits such as PLLs when they are not in use. For example, a PLL that is used in a data transmission circuit can be turned off during intervals when data is not being transmitted, such as between bursts of data. However, turning off such a PLL when data is not being transmitted requires that the PLL be powered up and achieve phase lock quickly each time another burst of data is to be transmitted. At least three factors are known to impact PLL power-up time. One such factor is that, as analog circuitry is powered up, time must be allocated for analog voltages and currents to stabilize. Another factor is that the PLL must start the process of frequency and phase locking to the reference clock. Still another factor is that the PLL system response is commonly optimized for a normal operational mode of the PLL (e.g., frequency synthesis, data transmission or recovery, etc.), and the system response that is optimal for the normal operational mode of the PLL is generally not also optimal for the period or mode in which the PLL is powering up and locking to the reference clock, as the loop dynamics (e.g., closed loop bandwidth, damping, etc.) differ during these two modes.
Phase-locked loops having switchable operating characteristics are known. For example, PLLs having adjustable settings are known that allow PLL parameters such as bandwidth and damping to be changed. However, such PLLs commonly only allow tuning of such parameters over a narrow range centered at the values to which the parameters are optimized for the normal operational mode of the PLL. Gain factors of, for example, 50 to 100 are needed to reduce PLL power-up time by an amount that is useful in a data transmission system, but conventional adjustable-gain PLLs can only be adjusted by much smaller gain factors. Adjustable-gain PLLs having a wide adjustment range are known, but they suffer from a number of drawbacks. For example, the very large transistors that are included in some adjustable-gain PLLs consume a large amount of power, occupy a large amount of integrated circuit die area, and induce large parasitic effects such as capacitance and leakage currents that can degrade PLL performance in normal operation.